COMMONLY USED IC COUNTERS AND REGISTERS BELONGING TO TTL CMOS & ECL LOGIC FAMILIES

A Table of Commonly used IC counters and registers belonging to the TTL, CMOS and ECL logic families


Type Number Function Logic FAMILY

7490 Decade counter TTL
7491 Eight-bit shift register (serial-in/serial-out) TTL
7493 Four-bit binary counter TTL
74160 BCD decade counter with asynchronous CLEAR TTL
74161 Four-bit binary counter with asynchronous CLEAR TTL
74162 BCD decade counter with synchronous CLEAR TTL
74163 Four-bit binary counter with synchronous CLEAR TTL

74164 Eight-bit shift register (serial-in/parallel-out) TTL
74165 Eight-bit shift register (parallel-in/serial-out)
74166 Eight-bit shift register (parallel-in/serial-out) TTL
74178 Four-bit parallel access shift register TTL
74190 Presettable BCD decade UP/DOWN counter TTL
74191 Presettable four-bit binary UP/DOWN counter TTL
74192 Presettable BCD decade UP/DOWN counter TTL
74193 Presettable four-bit binary UP/DOWN counter TTL
74194 Four-bit right/left universal shift register TTL
74198 Eight-bit universal shift register (parallel-in/parallel-out bidirectional) TTL
74199 Eight-bit universal shift register (parallel-in/parallel-out bidirectional) TTL
74290 Decade counter TTL
74293 Four-bit binary counter TTL
74390 Dual decade counter TTL
74393 Dual four-bit binary counter TTL
4014 B Eight-bit static shift register CMOS
(synchronous parallel or serial-in/serial-out)
4015 B Dual four-bit static shift register CMOS
(serial-in/parallel-out)
4017 B Five-stage Johnson counter CMOS
4021 B Eght-bit static shift register CMOS
(asynchronous parallel-in or synchronous serial-in/serial-out)
4029 B Synchronous presettable four-bit UP/DOWN counter CMOS
4035 B Four-bit universal shift register CMOS
40160 B Decade counter with asynchronous CLEAR CMOS
40161 B Binary counter with asynchronous CLEAR CMOS
40162 B Decade counter CMOS
40163 B Binary Counter CMOS
40192 B Presettable BCD UP/DOWN counter CMOS
40193 B Presettable Binary UP/DOWN counter CMOS
4510 B Presettable UP/DOWN BCD counter CMOS
4518 B Dual four-bit decade counter CMOS
4520B Dual four-bit binary counter CMOS
4522 B Four-bit BCD programmable divide-by-N counter CMOS
4722 B Programmable counter/timer CMOS
4731 B Quad 64-bit static shift register CMOS
MC 10136 Universal hexadecimal counter ECL
MC 10137 Universal decade counter ECL
MC 10141 Four-bit universal shift register ECL
MC 10154 Binary counter (four-bit) ECL
MC 10178 Four-bit binary counter ECL

CMOS GATES BASIC AND TUTORIALS

WHAT ARE CMOS GATES? HOW CMOS GATES WORK?


CMOS gates are based on simple modifications to the CMOS inverter.

Figure 8.18(a) and Figure 8.18(b) show that the CMOS NOR and NAND gates are essentially CMOS inverters in which the load and driving transistor are replaced by series or parallel combinations (as appropriate) of PMOS andNMOStransistors, respectively.

Suppose the NOR gate of Fig. 8.18(a) is to have the same VDD and Vinv as the CMOS inverter of Fig. 8.17(a), then the equivalent Zpu and Zpd for the NOR gate should equal those for the inverter.

Since only one of the parallel pull-down transistors needs be on in the NOR to ensure VO = 0V, ZI = Zpd = 1/2 , as for the inverter. For the series load, however, ZL = 1/10 to give equivalent Zpu = 1/5 .

If the NAND gate of Fig. 8.18(b) is to have the same Vinv as the said inverter, similar arguments lead to ZI = 1/4 and ZL = 1/5 for the NAND.

Thus, KR = 0.4 for the inverter, 0.2 for the NOR, and 0.8 (closer to unity) for NAND. Hence, NAND is the standard gate in CMOS.

Another way of putting this is that for the given Z values, if the channel length L is constant, then the widths of the loads for the inverter, NOR, and NAND are in the ratio 1:2:1.

Thus, the NOR requires more chip area, and this larger area requirement increases with the number of inputs.

CMOS INVERTERS BASIC AND TUTORIALS

WHAT ARE CMOS INVERTERS? APPLICATION OF CMOS INVERTERS

As shown in Fig. 8.17(a), the CMOS inverter consists of an enhancement NMOS as the driving transistor, and a complementary enhancement PMOS load transistor. The driving transistor is off when Vin is low, and the load transistor is off when Vin is high. 

Thus, one of the two series transistors is always off (equivalently, drain current and power dissipation are zero) except during switching,when both transistors are momentarily on. The resulting low-power dissipation is an important CMOS advantage and makes it an attractive alternative in VLSI design. 

NMOS circuits are ratioed in the sense that the pull up never turns off, and VOL is determined by the inverter ratio. CMOS is ratioless in this sense, since VOL is always the negative rail. If one desires equal sourcing and sinking currents, however, the pull-up device must be wider than the pull-down device by the ratio of the electron-to-hole mobilities, typically about 2.5 to 1. 

This also gives a symmetrical voltage transfer curve, with the voltage at which Vin = VO having a value of VDD/2. This voltage is referred to as the inverter voltage Vinv.

The voltage transfer for the CMOS inverter is shown in Fig. 8.17(b). Note that the voltage transfer characteristic approaches that of the ideal logic inverter. These characteristics are best obtained with computer circuit simulation programs. 

As with the depletion load NMOS inverter, useful insights may be gained by performing an analytical solution. The analysis proceeds as previously described for the depletion load NMOS inverter. 

Note that the VTC of Fig. 8.17(b) has been divided into regions as in Fig. 8.15(a). In each region, the appropriate expressions for the load and driving transistor drain currents are equated so that VO can be computed for any given Vin. 

To find VI L and VI H, the condition that dVO/dVin = −1 at such critical voltages is applied to the drain current equation.Note that the drain current equations for the PMOS are the same as for NMOS, except for reverse voltage polarities for the PMOS.