CASCADING BCD COUNTERS BASIC INFORMATION

BCD counters are used when the application involves the counting of pulses and the result of counting is to be displayed in decimal. A single-stage BCD counter counts from 0000 (decimal equivalent ‘0’) to 1001 (decimal equivalent ‘9’) and thus is capable of counting up to a maximum of nine pulses.

The output in a BCD counter is in binary coded decimal (BCD) form. The BCD output needs to be decoded appropriately before it can be displayed. Decoding a counter has been discussed in the previous section.

Coming back to the question of counting pulses, more than one BCD counter stage needs to be used in a cascade arrangement in order to be able to count up to a larger number of pulses. The number of BCD counter stages to be used equals the number of decimal digits in the maximum number of pulses we want to count up to.

With a maximum count of 9999 or 3843, both would require a four-stage BCD counter arrangement with each stage representing one decimal digit.

Figure 11.21 shows a cascade arrangement of four BCD counter stages.

The arrangement works as follows. Initially, all four counters are in the all 0s state. The counter representing the decimal digit of 1’s place is clocked by the pulsed signal that needs to be counted.

The successive flip-flops are clocked by the MSB of the immediately previous counter stage. The first nine pulses take 1’s place counter to 1001. The tenth pulse resets it to 0000, and ‘1’ to ‘0’ transition at the MSB of 1’s place counter clocks 10’s place counter. 10’s place counter gets clocked on every tenth input clock pulse.

On the hundredth clock pulse, the MSB of 10’s counter makes a ‘1’ to ‘0’ transition which clocks 100’s place counter. This counter gets clocked on every successive hundredth input clock pulse. On the thousandth input clock pulse, the MSB of 100’s counter makes ‘l’ to ‘0’ transition for the first time and clocks 1000’s place counter.

This counter is clocked thereafter on every successive thousandth input clock pulse. With this background, we can always tell the output state of the cascade arrangement. For example, immediately after the 7364th input clock pulse, the state of 1000’s, 100’s, 10’s and 1’s BCD counters would respectively be 0111, 0011, 0110 and 0100.

DESIGNING COUNTERS WITH ARBITRARY SEQUENCES BASICS

So far we have discussed different types of synchronous and asynchronous counters. A large variety of synchronous and asynchronous counters are available in IC form, and some of these have been mentioned and discussed in the previous sections.

The counters discussed hitherto count in either the normal binary sequence with a modulus of 2N or with slightly altered binary sequences where one or more of the states are skipped. The latter type of counter has a modulus of less than 2N , N being the number of flip-flops used.

Nevertheless, even these counters have a sequence that is either upwards or downwards and not arbitrary. There are applications where a counter is required to follow a sequence that is arbitrary and not binary.

As an example, an MOD-10 counter may be required to follow the sequence 0000, 0010, 0101, 0001, 0111, 0011, 0100, 1010, 1000, 1111, 0000, 0010 and so on. In such cases, the simple and seemingly obvious feedback arrangement with a single NAND gate discussed in the earlier sections of this chapter for designing counters with a modulus of less than 2N cannot be used.

There are several techniques for designing counters that follow a given arbitrary sequence. In the present section, we will discuss in detail a commonly used technique for designing synchronous counters using J-K flip-flops or D flip-flops.

The design of the counters basically involves designing a suitable combinational logic circuit that takes its inputs from the normal and complemented outputs of the flip-flops used and decodes the different states of the counter to generate the correct logic states for the inputs of the flip-flops such as J, K, D, etc.

But before we illustrate the design procedure with the help of an example, we will explain what we mean by the excitation table of a flip-flop and the state transition diagram of a counter. An excitation table in fact can be drawn for any sequential logic circuit, but, once we understand what it is in the case of a flip-flop, which is the basic building block of sequential logic, it would be much easier for us to draw the same for more complex sequential circuits such as counters, etc.

ASYNCHRONOUS AND SYNCHRONOUS COUNTERS DIFFERENCE BASIC AND TUTORIALS

To divide the counters we will look at into two types: asynchronous and synchronous. When used with respect to counters ~ these adjectives describe whether the flip-flops holding the states of the circuit are all clocked together (i.e. synchronously) by a master clock or rather asynchronously, with each flip-flop clocked by the one preceding it.

Asynchronous counters:
a. are also known as ripple counters;
b. are very simple;
c. use the minimum possible hardware (logic gates); employ flip-flops connected serially, with each one triggering (clocking) the next;

d. have an overall count which 'ripples' through, meaning the overall operation
is relatively slow;
e. require virtually no design.


Synchronous counters:
a. use interconnected flip-flops, but all are clocked together by the system clock;
b. use the outputs from the flip-flops, to determine the next states of the following flip-flops (rather than simply clocking them);
c. require no settling time due to rippling (as all flip-flops are clocked synchronously);
d. need designing, to determine how the present state of the circuit must be used to determine the next state (i.e. count);
e.  usually need more logic gates for their implementation.

Although we will not consider such circuits it is possible to design hybrid asynchronous/synchronous counters (e.g. two synchronous four-bit counters connected asynchronously to produce an eight-bit hybrid) that possess some of the advantages of both types and which are appropriate in some applications.

Due to their universal use in logic circuits, counters are widely available as logic elements in a wide range of forms. These often include clear and preset facilities (which can be used to load a particular count state), and up-down counts available within the same device.

Because the design of binary counters is largely intuitive the approach we will take is to firstly consider simple circuits that act as mod-2" counters, and then how they must be modified to produce a general mod-N count.