Showing posts with label Thyristor. Show all posts
Showing posts with label Thyristor. Show all posts

THYRISTORS DEFINITION AND BASIC INFORMATION TUTORIALS


WHAT ARE THYRISTORS? INFORMATION ABOUT THYRISTORS

Thyristors (or silicon controlled rectifiers) are three-terminal devices which can be used for switching and a.c. power control. Thyristors can switch very rapidly from a conducting to a nonconducting state. 


 
In the off state, the thyristor exhibits negligible leakage current, while in the on state the device exhibits very low resistance. This results in very little power loss within the thyristor even when appreciable power levels are being controlled. 

Once switched into the conducting state, the thyristor will remain conducting (i.e. it is latched in the on state) until the forward current is removed from the device. In d.c. applications this necessitates the interruption (or disconnection) of the supply before the device can be reset into its non-conducting state. 

Where the device is used with an alternating supply, the device will automatically become reset whenever the main supply reverses. The device can then be triggered on the next half-cycle having correct polarity to permit conduction. 

Like their conventional silicon diode counterparts, thyristors have anode and cathode connections; control is applied by means of a gate terminal (see Fig. 5.13). 

The device is triggered into the conducting (on state) by means of the application of a current pulse to this terminal. The effective triggering of a thyristor requires a gate trigger pulse having a fast rise time derived from a low-resistance source. 

Triggering can become erratic when insufficient gate current is available or when the gate current changes slowly. Table 5.4 summarizes the characteristics of several common thyristors.


LATCH UP PARASITIC THYRISTOR BASIC AND TUTORIALS


WHAT IS A LATCH UP PARASITIC THYRISTOR?

A portion of the minority carriers injected into the drift region from the collector of an IGBT flows directly to the emitter terminal. The negative charge of electrons in the inversion layer attracts the majority of holes and generates the lateral component of hole current through the p-type body layer as shown in Fig. 7.10.



This lateral current flow develops a voltage drop across the spreading resistance of the p-base region, which forward-biases the base-emitter junction of the npnparasitic BJT. By designing a small spreading resistance, the voltage drop is lower than the built-in potential and therefore the parasitic thyristor between the p‡-collector region, nÿ-drift region, p-base region, and n‡-emitter does not latch up.

Larger values of on-state current density produce a larger voltage drop, which causes injection of electrons from the emitter region into the p-base region and hence turn-on of the npn-transistor.

When this occurs the pnp-transistor will turn on, and therefore the parasitic thyristor will latch up and the gate loses control over the collector current.

Under dynamic turn-off conditions the magnitude of the lateral hole current flow increases and latch-up can occur at lower on-state currents compared to the static condition. The parasitic thyristor latches up when the sum of the current gains of the npn- and pnp-transistors exceeds one.

When the gate voltage is removed from IGBT with a clamped inductive load, its MOSFET component turns off and reduces the MOSFET current to zero very rapidly. As a result the drainsource voltage rises rapidly and is supported by the junction between the nÿ-drift region and the p-base region.

The drift region has a lower doping and therefore the depletion layer extends more in the drift region. Hence, the current gain of the pnp-transistor portion, apnp, increases and a greater portion of the injected holes into the drift region will be collected at the junction of p-base and nÿ-drift regions.

Therefore, the magnitude of the lateral hole current increases, which increases the lateral voltage drop. As a result the parasitic thyristor will latch up even if the on-state current is less than the static latch-up
value.

Reducing the gain of the npn- or pnp-transistors can prevent the parasitic thyristor latch-up. A reduction in the gain of the pnp-transistor increases the IGBT on-state voltage drop. Therefore, in order to prevent the parasitic thyristor latch up it is better to reduce the gain of the npn-transistor component of IGBT.

Reduction of carrier lifetime, use of buffer layer, and use of deep p‡-diffusion improve the latch-up immunity of IGBT. However, inadequate extension of the p‡-region may fail to prevent the device from latch-up.

Also, care should be taken that the p‡-diffusion does not extend into the MOS channel because this causes an increase in the MOS threshold voltage.