DIODE RATINGS BASIC AND TUTORIALS

RATINGS OF DIODES BASIC INFORMATION
What Are The Ratings Of Diodes?

In addition to forward voltage drop (Vf ) and peak inverse voltage (PIV), there are many other ratings of diodes important to circuit design and component selection. Semiconductor manufacturers provide
detailed specifications on their products { diodes included { in publications known as datasheets.
Datasheets for a wide variety of semiconductor components may be found in reference books and on the internet. I personally prefer the internet as a source of component specifications because all the data obtained from manufacturer websites are up-to-date.

A typical diode datasheet will contain figures for the following parameters:

Maximum repetitive reverse voltage = VRRM, the maximum amount of voltage the diode can withstand in reverse-bias mode, in repeated pulses. Ideally, this figure would be infinite.

Maximum DC reverse voltage = VR or VDC, the maximum amount of voltage the diode can withstand in reverse-bias mode on a continual basis. Ideally, this figure would be infinite.

Maximum forward voltage = VF , usually specified at the diode's rated forward current. Ideally, this figure would be zero: the diode providing no opposition whatsoever to forward current. In reality, the forward voltage is described by the "diode equation."

Maximum (average) forward current = IF(AV ), the maximum average amount of current the
diode is able to conduct in forward bias mode. This is fundamentally a thermal limitation: how
much heat can the PN junction handle, given that dissipation power is equal to current (I) multiplied
by voltage (V or E) and forward voltage is dependent upon both current and junction temperature.
Ideally, this figure would be infinite.

Maximum (peak or surge) forward current = IFSM or if(surge), the maximum peak amount of current the diode is able to conduct in forward bias mode. Again, this rating is limited by the diode junction's thermal capacity, and is usually much higher than the average current rating due to thermal inertia (the fact that it takes a finite amount of time for the diode to reach maximum temperature for a given current). Ideally, this figure would be infinite.

Maximum total dissipation = PD, the amount of power (in watts) allowable for the diode to dissipate, given the dissipation (P=IE) of diode current multiplied by diode voltage drop, and also the dissipation (P=I2R) of diode current squared multiplied by bulk resistance. Fundamentally limited by the diode's thermal capacity (ability to tolerate high temperatures).

Operating junction temperature = TJ , the maximum allowable temperature for the diode's PN junction, usually given in degrees Celsius (oC). Heat is the "Achilles' heel" of semiconductor devices: they must be kept cool to function properly and give long service life.

Storage temperature range = TSTG, the range of allowable temperatures for storing a diode (un- powered). Sometimes given in conjunction with operating junction temperature (TJ ), because the maximum storage temperature and the maximum operating temperature ratings are often identical. If anything, though, maximum storage temperature rating will be greater than the maximum operating temperature rating.

Thermal resistance = R(£), the temperature difierence between junction and outside air (R(£)JA) or between junction and leads (R(£)JL) for a given power dissipation. Expressed in units of degrees Celsius per watt (oC/W).

Ideally, this figure would be zero, meaning that the diode package was a perfect thermal conductor and radiator, able to transfer all heat energy from the junction to the outside air (or to the leads) with no difierence in temperature across the thickness of the diode package.

A high thermal resistance means that the diode will build up excessive temperature at the junction (where it's critical) despite best efiorts at cooling the outside of the diode, and thus will limit its maximum power dissipation.

Maximum reverse current = IR, the amount of current through the diode in reverse-bias operation, with the maximum rated inverse voltage applied (VDC). Sometimes referred to as leakage current.

Ideally, this figure would be zero, as a perfect diode would block all current when reverse- biased. In reality, it is very small compared to the maximum forward current.

Typical junction capacitance = CJ , the typical amount of capacitance intrinsic to the junction, due to the depletion region acting as a dielectric separating the anode and cathode connections. This is usually a very small figure, measured in the range of picofarads (pF).

Reverse recovery time = trr, the amount of time it takes for a diode to "turn ofi" when the voltage across it alternates from forward-bias to reverse-bias polarity. Ideally, this figure would be zero: the diode halting conduction immediately upon polarity reversal.

For a typical rectifier diode, reverse recovery time is in the range of tens of microseconds; for a "fast switching" diode, it may only be a few nanoseconds.

Most of these parameters vary with temperature or other operating conditions, and so a single figure fails to fully describe any given rating. Therefore, manufacturers provide graphs of component ratings plotted against other variables (such as temperature), so that the circuit designer has a better idea of what the device is capable of.

LATCH UP PARASITIC THYRISTOR BASIC AND TUTORIALS

WHAT IS A LATCH UP PARASITIC THYRISTOR?

A portion of the minority carriers injected into the drift region from the collector of an IGBT flows directly to the emitter terminal. The negative charge of electrons in the inversion layer attracts the majority of holes and generates the lateral component of hole current through the p-type body layer as shown in Fig. 7.10.

This lateral current flow develops a voltage drop across the spreading resistance of the p-base region, which forward-biases the base-emitter junction of the npnparasitic BJT. By designing a small spreading resistance, the voltage drop is lower than the built-in potential and therefore the parasitic thyristor between the p‡-collector region, nÿ-drift region, p-base region, and n‡-emitter does not latch up.

Larger values of on-state current density produce a larger voltage drop, which causes injection of electrons from the emitter region into the p-base region and hence turn-on of the npn-transistor.

When this occurs the pnp-transistor will turn on, and therefore the parasitic thyristor will latch up and the gate loses control over the collector current.

Under dynamic turn-off conditions the magnitude of the lateral hole current flow increases and latch-up can occur at lower on-state currents compared to the static condition. The parasitic thyristor latches up when the sum of the current gains of the npn- and pnp-transistors exceeds one.

When the gate voltage is removed from IGBT with a clamped inductive load, its MOSFET component turns off and reduces the MOSFET current to zero very rapidly. As a result the drainsource voltage rises rapidly and is supported by the junction between the nÿ-drift region and the p-base region.

The drift region has a lower doping and therefore the depletion layer extends more in the drift region. Hence, the current gain of the pnp-transistor portion, apnp, increases and a greater portion of the injected holes into the drift region will be collected at the junction of p-base and nÿ-drift regions.

Therefore, the magnitude of the lateral hole current increases, which increases the lateral voltage drop. As a result the parasitic thyristor will latch up even if the on-state current is less than the static latch-up

value.

Reducing the gain of the npn- or pnp-transistors can prevent the parasitic thyristor latch-up. A reduction in the gain of the pnp-transistor increases the IGBT on-state voltage drop. Therefore, in order to prevent the parasitic thyristor latch up it is better to reduce the gain of the npn-transistor component of IGBT.

Reduction of carrier lifetime, use of buffer layer, and use of deep p‡-diffusion improve the latch-up immunity of IGBT. However, inadequate extension of the p‡-region may fail to prevent the device from latch-up.

Also, care should be taken that the p‡-diffusion does not extend into the MOS channel because this causes an increase in the MOS threshold voltage.