### CMOS INVERTERS BASIC AND TUTORIALS

WHAT ARE CMOS INVERTERS? APPLICATION OF CMOS INVERTERS

As shown in Fig. 8.17(a), the CMOS inverter consists of an enhancement NMOS as the driving transistor, and a complementary enhancement PMOS load transistor. The driving transistor is off when Vin is low, and the load transistor is off when Vin is high.

Thus, one of the two series transistors is always off (equivalently, drain current and power dissipation are zero) except during switching,when both transistors are momentarily on. The resulting low-power dissipation is an important CMOS advantage and makes it an attractive alternative in VLSI design.

NMOS circuits are ratioed in the sense that the pull up never turns off, and VOL is determined by the inverter ratio. CMOS is ratioless in this sense, since VOL is always the negative rail. If one desires equal sourcing and sinking currents, however, the pull-up device must be wider than the pull-down device by the ratio of the electron-to-hole mobilities, typically about 2.5 to 1.

This also gives a symmetrical voltage transfer curve, with the voltage at which Vin = VO having a value of VDD/2. This voltage is referred to as the inverter voltage Vinv.

The voltage transfer for the CMOS inverter is shown in Fig. 8.17(b). Note that the voltage transfer characteristic approaches that of the ideal logic inverter. These characteristics are best obtained with computer circuit simulation programs.

As with the depletion load NMOS inverter, useful insights may be gained by performing an analytical solution. The analysis proceeds as previously described for the depletion load NMOS inverter.

Note that the VTC of Fig. 8.17(b) has been divided into regions as in Fig. 8.15(a). In each region, the appropriate expressions for the load and driving transistor drain currents are equated so that VO can be computed for any given Vin.

To find VI L and VI H, the condition that dVO/dVin = −1 at such critical voltages is applied to the drain current equation.Note that the drain current equations for the PMOS are the same as for NMOS, except for reverse voltage polarities for the PMOS.