What are the Memory IC Failure Modes?
Memory IC Failure Modes Defined.

Memory ICs failures result in the inability to read or write data, erroneous data storage, unacceptable output levels, and slow access time. The specific failures that cause these problems are as follows:

Open and short circuits: can cause various problems from a single bit error to a catastrophic failure of the whole device.

Open decoder circuits: cause addressing problems to the memory.

Multiple writes: writing one cell actually writes to that cell and other cells (multiple write and address uniqueness problems).

Pattern sensitivity: the contents of a cell become complemented due to read and write operations in electrically adjacent cells (cell disturbances, adjacent cell disturbances, column disturbances, adjacent column disturbances, row disturbance, adjacent row disturbance).

Write recovery: the access time of the device may be slower than specified when each read cycle is preceded by a write cycle, or a number of write cycles.

Address decoder switching time: this time can vary depending on the state of the address decoder prior to switching and on the state to which the decoder is switching.

Sense amplifier sensitivity: memory information may be incorrect after reading a long series of similar data bits followed by a single transition of the opposite data value.

Sleeping sickness: the memory loses information in less than the specified hold time (for DRAMs).

Refresh problems (may be static or dynamic): the static refresh test checks the data contents after the device has been inactive during a refresh. In dynamic refresh, the device remains active and some cells are refreshed. All cells are then tested to check whether the data in the nonrefreshed cells is still correct.

Special tests are needed for memory devices to insure the integrity of every memory bit location. These functional tests are composed of four basic tests, pattern tests, background tests, timing test, and voltage level tests.

Memory tests cannot be specified to test each part 100% as a RAM can contain any one of 2N different data patterns and can be addressed in N factorial (N!) address sequences without using the same address twice.

Test times shown may be extremely long for some high-density memory devices; a GALPAT test for a 4 M DRAM would take 106 days to execute. It is easy to see how impractical it is to overspecify device testing. Any test plan should be developed along with the supplier of the memory devices you are to purchase.

System level tests may use bit-map graphics where the status of the memory cells is displayed on the cathode ray tube (CRT) display of the system (i.e., failing bits show up as a wrong color). Various patterns are read into the memory and the CRT may be configured to show 1 cell equivalent to one pixel (a picture element) or compressed to show 4, 16, or 64 cells per pixel depending on the number of pixels available and the memory size.

Zoom features can be used to scale the display for close examination of failing areas of the memory. Note, in large memory intensive systems, consider using error correction codes to correct hard (permanent failure) and soft errors (i.e., alpha particle upsets, a single upset that does not occur again).

One vendor of video RAMs estimates a soft error rate of a 1 Meg part of 3.9 FITs (at a 500-ns cycle time with Vcc at 4.5 V, and a 4 Meg DRAM error rate of 41 FITs (at a 90% confidence level, 5 Vcc operation with 15.625-μs cycle (refresh) rate). Soft error rates are dependent on cycle time and operating voltage; the lower the voltage and faster the cycle time, the higher the failure in time rate.

One thousand FITs equals 1 PPM (1 failure in 106 h), which equals 0.1%/1000 (0.1% failures every 1000 h). When calculating soft error rates, add the refresh mode rate and the active mode rate, which can be determined from acceleration curves provided by the manufacturer.

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